FIG. 1 shows a construction of a prior art dual-port memory. In FIG. 1, reference numeral 1 designates a memory array which is capable of being randomly accessed, and this memory array 1 includes a plurality of memory cells for storing information in an arrangement of m rows and n columns. The reference numeral 2 designates a latch-appended row decoder for selecting memory cells arranged at the respective rows of the memory cell array 1. The reference numeral 3 designates a latch-appended column decoder for selecting memory cells arranged on the respective columns. The reference numeral 4 designates an input/output data control circuit for controlling the reading-out or writing-in of information from the memory cells of the memory array 1. The reference numeral 5 designates a serial access memory to which information in the memory cells at the row selected by the row decoder 2 is input in parallel and output serially. Furthermore, the reference character Ai designates i address inputs which are input to the row decoder 2 and the column decoder 3. The reference character RAS (Row Address Strobe signal) designates a trigger signal for latching the row address, and the reference character CAS (Column Address Strobe signal) designates a trigger signal for latching the column address. The reference character RD designates a reading-out control signal which is input to the I/O data control circuit 4. The reference character WR designates a writing-in control signal which is input to the I/O data control circuit 4. The reference character D designates a data I/O line for outputting information from the memory array 1 and inputting information to the memory array 1 through the I/O data control circuit 4. The reference character DT designates a data transfer control signal which is input to the serial access memory 5. The reference character SC designates a serial clock which is input to the serial access memory 5. The reference character SO designates a serial output through which data is output serially from a serial access memory 5 as data stored in the row of the memory array 1.
The operation of this device will be described with reference to FIG. 2.
When this prior art dual-port memory is operated similarly as usual dynamic RAMs, as address inputs a row address and column address are time sequentially input to the row decoder 2 and the column decoder 3, and they are respectively latched at the internal registers by trigger signals of RAS and CAS, respectively. These row and column addresses are decoded by the decoders 2 and 3, respectively, and the reading-out and writing-in operations from the memory cell of the memory array 1 selected by these decoders 2 an 3 are conducted. When the signal RD is input to the I/O data control circuit 4, the reading-out operation is conducted in which information in the selected memory cell of the memory array 1 is output to the I/O data line D through the I/O data control circuit 4, and when the signal WR is input to the I/O data control circuit 4, the writing-in operation is conducted in which information which is, input to the data I/O line D is input to the selected memory cell 1 through the I/O data control circuit 4.
Next, the operation of transferring data from the memory array 1 to the serial access memory 5 and outputting information in the memory cell at a row of the memory array 1 to the serial output SO will be described.
As shown in FIG. 2, the signal DT is at an "H" level at the rising edge of RAS thereby to indicate the data transfer mode, and the row address r of the row to which the data is to be transferred is input to the address line Ai. The transfer of data from the memory array 1 to the serial access memory 5 is executed at the falling edge of the signal DT. That are the memory cells on a row of the memory array 1 is selected by the row decoder 2, and information in the memory cells of that row selected by the falling edge of the signal DT are transferred in parallel to the serial access memory 5. Then, all or a portion of the column data of a selected column are transferred to the serial access memory 5 in parallel.
Next, when the clock SC is input to the serial access memory 5, the parallel data in the serial access memory 5 are output to the terminal SO serially at each clock.
In the prior art dual-port memory having such a construction, it is necessary to synchronize operation with the serial clocks in order to transfer new row data along with the outputting of signals from the serial access memory successively, and this unavoidably makes the control complicated.